1. Field of the Invention
The present invention relates to a buffer, and in particular to a method and apparatus that controls and modulates the amount of hysteresis in a buffer in response to changes in the operating conditions.
2. Art Background
In the design of digital circuits, the noise immunity of the circuit must be considered. Noise in a digital circuit or system can cause, for example, a switching circuit to erroneously transition from one logic level to another. A significant contributor to noise experienced by a digital circuit is on-chip generated noise. On-chip generated noise can be produced by the switching of output drivers which cause voltage spikes on the power supply busses. In addition, the operating conditions of the digital circuit can increase or reduce the amount of noise generated. High noise operating conditions, that is, operating conditions which comprise fast transistor parameters (such as high conductance), high power supply voltages and low operating temperatures, increase the incidence of on-chip generated noise. Conversely, low noise operating conditions, that is, operating conditions which comprise slow transistor parameters (such as low conductance), low power supply voltages and high operating temperatures, reduce the incidence of on-chip generated noise.
To reduce the negative effects of noise in a digital buffer circuit, hysteresis is often employed. Hysteresis provides a buffer with a degree of noise immunity at the expense of introducing a constant delay into the speed of the buffer circuitry. A switching buffer with hysteresis will transition from a first logic state to a second logic state as an input signal applied to the buffer reaches a predetermined voltage level called the direct current (DC) trip point. To transition the switching buffer back from the second logic state to the first logic state the input signal transitions at a voltage offset from the DC trip point. The difference in transition points is the amount of hysteresis in the circuit and provides the switching buffer with noise immunity and reduces the occurrence of erroneous switching. However, the circuit elements that produce hysteresis in the switching buffer also introduce a delay into the switching speed of the buffer. The hysteresis delay is present whether the switching buffer is operating under high noise operating conditions where hysteresis is needed, low noise operating conditions where hysteresis is not needed, or any operating point in between where some degree of hysteresis is needed.
FIG. 1 illustrates a switching circuit with hysteresis commonly referred to as a Schmitt Trigger. The circuit contains a complimentary metal oxide semiconductor (CMOS) NOR gate with input signals VIN and LOW POWER. The CMOS NOR gate has p-channel MOSFETs 2 and 4 coupled to n-channel MOSFETs 6, 8 and 14. A feedback n-channel MOSFET 10 is coupled to the out-put 12 of the CMOS NOR gate. CMOS current buffers (shown as inverters) 16 and 18 are coupled to out-put 12. CMOS inverters 16 and 20 provide VOUT' and VOUT. When the LOW POWER signal is a low logic level, hysteresis is provided by the n-channel MOSFETs 8 and 10. As VIN transitions from a high logic level to a low logic level the CMOS NOR gate transitions at a predetermined DC trip point. As VIN transitions from a low logic level to a high logic level n-channel MOSFETs 8 and 10 increase the source voltage on transistor 6 which will effectively raise the high logic level DC trip point.
FIG. 2 illustrates a second technique for generating hysteresis in a buffer circuit. Again, the circuit contains a CMOS NOR gate having inputs VIN and LOW POWER. The CMOS NOR gate has p-channel MOSFETs 40 and 44 coupled to n-channel MOSFETs 46 and 48. A p-channel MOSFET 42 is coupled to p-channel MOSFET 40. CMOS inverter 50 is coupled is coupled to output VOUT, provides VOUT and enables p-channel MOSFET 42. When the LOW POWER signal is a low logic level, hysteresis is provided when VIN transitions from a high logic level to a low logic level at a predetermined DC trip point. This causes CMOS inverter 50 to transition and enable p-channel transistor 42. As VIN transitions from a high logic level to a low logic level p-channel MOSFET 42 produces a voltage transition point greater than the DC trip point.
In the prior art circuits illustrated in FIG. 1 and FIG. 2, hysteresis is present whenever the buffer is enabled. Therefore these circuits introduce delays in the operating speeds of the buffers regardless of whether the operating conditions of the buffer comprise high noise operating conditions, low noise operating conditions, or intermediate noise operating conditions. Therefore the buffers with hysteresis suffer a speed penalty by employing hysteresis during operating conditions when it is not required. Moreover, these circuits cannot detect and control the amount of hysteresis in the buffer as a function of variations in operating conditions.